The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, in semiconductor technologies, a plurality of photomasks (masks) are formed with predesigned IC patterns. The plurality of masks are used during lithography processes to transfer predesigned IC patterns into a plurality of exposure fields on a semiconductor wafer. That is, once a semiconductor wafer has been fabricated, it contains many copies of the same integrated circuit on a plurality of dies. Traditionally, a fabricated semiconductor wafer undergoes evaluative testing to ensure the integrated circuits are formed correctly and that they operate in a desired manner. This testing may be performed using a plurality of test structures (or process control monitors) formed on the wafer. Because space is at a premium on a production wafer, these test structures are commonly formed in the scribe line region between dies. However, forming test structures in a scribe line region has its drawbacks. For instance, a scribe line region may need to have a certain width to accommodate various test structures, thereby limiting the space on a wafer in which dies may be formed. Thus, although existing approaches have been satisfactory for their intended purposes, they have not been entirely satisfactory in all respects.